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 IS42S16100
512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
FEATURES
* Clock frequency: 200, 166, 143 MHz * Fully synchronous; all signals referenced to a positive clock edge * Two banks can be operated simultaneously and independently * Dual internal bank controlled by A11 (bank select) * Single 3.3V power supply * LVTTL interface * Programmable burst length - (1, 2, 4, 8, full page) * Programmable burst sequence: Sequential/Interleave * 2048 refresh cycles every 32 ms * Random column address every clock cycle * Programmable CAS latency (2, 3 clocks) * Burst read/write and burst read/single write operations capability * Burst termination by burst stop and precharge command * Byte controlled by LDQM and UDQM * Packages 400-mil 50-pin TSOP-II and 60-ball BGA * Lead-free package option * Available in Industrial Temperature FEBRUARY 2008
DESCRIPTION ISSI's 16Mb Synchronous DRAM IS42S16100 is
organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD DQ0 DQ1 GNDQ DQ2 DQ3 VDDQ DQ4 DQ5 GNDQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 GND DQ15 IDQ14 GNDQ DQ13 DQ12 VDDQ DQ11 DQ10 GNDQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 GND
PIN DESCRIPTIONS
A0-A11 A0-A10 A11 A0-A7 DQ0 to DQ15 CLK CKE CS RAS Address Input Row Address Input Bank Select Address Column Address Input Data DQ System Clock Input Clock Enable Chip Select Row Address Strobe Command CAS WE LDQM UDQM VDD GND VDDQ GNDQ NC Column Address Strobe Command Write Enable Lower Bye, Input/Output Mask Upper Bye, Input/Output Mask Power Ground Power Supply for DQ Pin Ground for DQ Pin No Connection
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
1
IS42S16100
PIN CONFIGURATION PACKAGE CODE: B 60 BALL FBGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)
1234567 A B C D E F G H J K L M N P R
PIN DESCRIPTIONS
A0-A10 A0-A7 A11 DQ0 to DQ15 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE LDQM, UDQM Vdd Vss Vddq Vssq NC Write Enable x16 Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection
VSS DQ15 DQ14 VSSQ DQ13 VDDQ DQ12 DQ11 DQ10 VSSQ DQ9 VDDQ DQ8 NC NC NC
DQ0
VDD
VDDQ DQ1 VSSQ DQ2 DQ4 DQ3
VDDQ DQ5 VSSQ DQ6 NC VDD LDQM RAS NC NC A0 A2 A3 DQ7 NC WE CAS CS NC A10 A1 VDD
NC UDQM NC CKE A11 A8 A6 VSS CLK NC A9 A7 A5 A4
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
PIN FUNCTIONS
Pin No. 20 to 24 27 to 32 Symbol A0-A10 Type Input Pin Function (In Detail) A0 to A10 are address inputs. A0-A10 are used as row address inputs during active command input and A0-A7 as column address inputs during read or write command input. A10 is also used to determine the precharge mode during other commands. If A10 is LOW during precharge command, the bank selected by A11 is precharged, but if A10 is HIGH, both banks will be precharged. When A10 is HIGH in read or write command cycle, the precharge starts automatically after the burst access. These signals become part of the OP CODE during mode register set command input. A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high, bank 1 is selected. This signal becomes part of the OP CODE during mode register set command input. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. The CKE input determines whether the CLK input is enabled within the device. When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid. When CKE is LOW, the device will be in either the power-down mode, the clock suspend mode, or the self refresh mode. The CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units using the LDQM and UDQM pins. LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device. RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. VddQ is the output buffer power supply. Vdd is the device internal power supply. GNdQ is the output buffer ground. GNd is the device internal ground.
19
A11
Input Pin
16 34
CAS CKE
Input Pin Input Pin
35 18
CLK CS
Input Pin Input Pin
2, 3, 5, 6, 8, 9, 11 12, 39, 40, 42, 43, 45, 46, 48, 49 14, 36
DQ0 to DQ15 LDQM, UDQM
DQ Pin
Input Pin
17 15 7, 13, 38, 44 1, 25 4, 10, 41, 47 26, 50
RAS WE VddQ Vdd GNdQ GNd
Input Pin Input Pin Power Supply Pin Power Supply Pin Power Supply Pin Power Supply Pin
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
3
IS42S16100
FUNCTIONAL BLOCK DIAGRAM
CLK CKE CS RAS CAS WE A11
COMMAND DECODER & CLOCK GENERATOR
ROW DECODER
MODE REGISTER
11
11
ROW ADDRESS BUFFER
2048
MEMORY CELL ARRAY
11
BANK 0
DQM
SENSE AMP I/O GATE
A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
REFRESH CONTROLLER
SELF REFRESH CONTROLLER
COLUMN ADDRESS BUFFER
BURST COUNTER
COLUMN ADDRESS LATCH
DATA IN BUFFER
16 16
256
COLUMN DECODER
8
DQ 0-15
8
256
SENSE AMP I/O GATE
REFRESH COUNTER
ROW DECODER
16
DATA OUT BUFFER
16
MULTIPLEXER
11
ROW ADDRESS LATCH
11
ROW ADDRESS BUFFER
2048
MEMORY CELL ARRAY
VDD/VDDQ GND/GNDQ
BANK 1
11
S16BLK.eps
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Vdd max Vddq ViN Vout Pd max Ics Topr Tstg
max
Parameters Maximum Supply Voltage Maximum Supply Voltage for Output Buffer Input Voltage Output Voltage Allowable Power Dissipation output Shorted Current operating Temperature Storage Temperature Com Ind.
Rating
Unit
-1.0 to +4.6 V -1.0 to +4.6 V -1.0 to +4.6 V -1.0 to +4.6 V 1 50 0 to +70 -40 to +85 W mA C C
-55 to +150 C
DC RECOMMENDED OPERATING CONDITIONS(2) (At Ta = 0 to +70C)
Symbol Vdd, Vddq Vih Vil Parameter Supply Voltage Input High Voltage(3) Input Low Voltage(4) Min. 3.0 2.0 -0.3 Typ. 3.3 -- -- Max. 3.6 Vdd + 0.3 +0.8 Unit V V V
CAPACITANCE CHARACTERISTICS(1,2) (At Ta = 0 to +25C, VDD = VDDQ = 3.3 0.3V, f = 1 MHz)
Symbol CiN1 CiN2 CI/O Parameter Input Capacitance: A0-A11 Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM) Data Input/Output Capacitance: DQ0-DQ15 Typ. -- -- -- Max. 4 4 5 Unit pF pF pF
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to GND. 3. Vih (max) = Vddq + 2.0V with a pulse width 3 ns.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
5
IS42S16100
DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter iil Input Leakage Current iol Voh Vol icc1 Test Condition Speed 0V ViN Vdd, with pins other than the tested pin at 0V Output Leakage Current Output is disabled, 0V Vout Vdd Output High Voltage Level iout = -2 mA Output Low Voltage Level iout = +2 mA Operating Current(1,2) One Bank Operation, CAS latency = 3 Com. -5 Burst Length=1 Com. -6 trc trc (min.) Com. -7 Iout = 0mA Ind. -6 Ind. -7 Precharge Standby Current CKE Vil (max) tck = tck (miN) Com. -- Ind. -- (In Power-Down Mode) tck = Com. -- Ind. -- Active Standby Current CKE Vih (miN) tck = tck (miN) -- (In Non Power-Down Mode) tck = Com. -- Ind. -- Operating Current tck = tck (miN) CAS latency = 3 Com. -5 (In Burst Mode)(1) Iout = 0mA Com. -6 Ind. -6 Com. -7 Ind. -7 CAS latency = 2 Com. -5 Com. -6 Ind. -6 Com. -7 Ind. -7 Auto-Refresh Current trc = trc (miN) CAS latency = 3 Com. -5 Com. -6 Ind. -6 Com. -7 Ind. -7 CAS latency = 2 Com. -5 Com. -6 Ind. -6 Com. -7 Ind. -7 Self-Refresh Current CKE 0.2V -- Min. -5 -5 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5 5 -- 0.4 170 160 140 170 160 3 4 2 -- 40 30 30 170 150 170 130 150 170 150 170 130 150 120 100 110 70 90 120 100 110 70 90 2 Unit A A V V mA
icc2p Icc2ps icc3N Icc3Ns icc4
mA
mA
mA
mA
icc5
mA
mA
icc6
mA
Notes: 1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time increases. Also note that a bypass capacitor of at least 0.01 F should be inserted between Vdd and GND for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents. 2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
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Rev. D 01/28/08
IS42S16100
AC CHARACTERISTICS(1,2,3)
Symbol Parameter tck3 tck2 tac3 tac2 tchi tcl toh3 toh2 tlz thz3 thz2 tds tdh tas tah tcks tckh tcka tcs tch trc tras trp trcd trrd tdpl3 tdpl2 tdal3 tdal2 tt tref Clock Cycle Time Access Time From CLK(4) CLK HIGH Level Width CLK LOW Level Width Output Data Hold Time Output LOW Impedance Time Output HIGH Impedance Time(5) Input Data Setup Time Input Data Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time CKE to CLK Recovery Delay Time Command Setup Time (CS, RAS, CAS, WE, DQM) Command Hold Time (CS, RAS, CAS, WE, DQM) Command Period (REF to REF / ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Active Command To Read / Write Command Delay Time Command Period (ACT [0] to ACT[1]) Input Data To Precharge Command Delay time CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 Min. 5 8 -- -- 2 2 2 2.5 0 -- -- 2 1 2 1 2 1 2 1 48 32 16 16 11 -- -- -5 Max. -- -- 5 6 -- -- -- -- -- 4 6 -- -- -- -- -- -- -- -- -- -- -- -- -- 2CLK 2CLK Min. 6 8 -- -- 2.5 2.5 2.0 2.5 0 -- -- 2 1 2 1 2 1 1CLK+3 2 1 54 36 18 16 12 2CLK 2CLK -6 Max. -- -- 5.5 6 -- -- -- -- -- 5.5 6 -- -- -- -- -- -- -- -- -- -- 100,000 -- -- -- -- -- Min. 7 8 -- -- 2.5 2.5 2.0 2.5 0 -- -- 2 1 2 1 2 1 1CLK+3 2 1 63 42 20 16 14 2CLK 2CLK -7 Max. -- -- 5.5 6 -- -- -- -- -- 5.5 6 -- -- -- -- -- -- -- -- -- -- 100,000 -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
1CLK+3 --
Input Data To Active / Refresh CAS Latency = 3 Command Delay time (During Auto-Precharge) CAS Latency = 2 Transition Time Refresh Cycle Time (2048)
2CLK+trp -- 2CLK+trp -- 1 -- 10 32
2CLK+trp -- 2CLK+trp -- 1 -- 10 32
2CLK+trp -- 2CLK+trp -- 1 -- 10 32
Notes: 1. When power is first applied, memory operation should be started 100 s after Vdd and Vddq reach their stipulated voltages. Also note that the power-on sequence must be executed before starting memory operation. 2. measured with tt = 1 ns. 3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between Vih (min.) and Vil (max.). 4. Access time is measured at 1.4V with the load shown in the figure below. 5. The time thz (max.) is defined as the time required for the output voltage to transition by 200 mV from Voh (min.) or Vol (max.) when the output is in the high impedance state.
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Rev. D 01/28/08
7
IS42S16100
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL -- -- tcac trcd trac trc tras trp trrd tccd tdpl tdal trbd twbd trql twdl tpql tqmd tdmd tmcd PARAMETER Clock Cycle Time Operating Frequency CAS Latency Active Command To Read/Write Command Delay Time RAS Latency (trcd + tcac) Command Period (REF to REF / ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Command Period (ACT[0] to ACT [1]) Column Command Delay Time (READ, READA, WRIT, WRITA) Input Data To Precharge Command Delay Time Input Data To Active/Refresh Command Delay Time (During Auto-Precharge) Burst Stop Command To Output in HIGH-Z Delay Time (Read) Burst Stop Command To Input in Invalid Delay Time (Write) Precharge Command To Output in HIGH-Z Delay Time (Read) Precharge Command To Input in Invalid Delay Time (Write) Last Output To Auto-Precharge Start Time (Read) DQM To Output Delay Time (Read) DQM To Input Delay Time (Write) Mode Register Set To Command Delay Time -5 5 200 3 3 6 9 6 3 2 1 2 5 3 0 3 0 -2 2 0 2 -6 6 166 3 3 6 9 6 3 2 1 2 5 3 0 3 0 -2 2 0 2 -7 7 143 3 3 6 9 6 3 2 1 2 5 3 0 3 0 -1 2 0 2 UNITS ns MHz cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
AC TEST CONDITIONS (Input/Output Reference Level: 1.4V) Output Load Input
tCHI
2.8V
tCK
tCL
CLK
1.4V 0.0V 2.8V
50 I/O +1.4V 50 pF
tCS
tCH
INPUT 1.4V
0.0V
tOH
tAC
1.4V 1.4V
OUTPUT
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
COMMANDS Active Command
CLK CKE HIGH CS RAS CAS WE A0-A9 A10
ROW
Read Command
CLK CKE HIGH CS RAS CAS WE A0-A9 A10
NO PRECHARGE BANK 1 COLUMN (1) AUTO PRECHARGE
ROW BANK 1
A11
BANK 0
A11
BANK 0
Write Command
CLK CKE HIGH CS RAS CAS WE A0-A9 A10
NO PRECHARGE BANK 1 COLUMN(1) AUTO PRECHARGE
Precharge Command
CLK CKE HIGH CS RAS CAS WE A0-A9
BANK 0 AND BANK 1
A10
BANK 0 OR BANK 1 BANK 1
A11
BANK 0
A11
BANK 0
Don't Care
Notes: 1. A8-A9 = Don't Care.
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Rev. D 01/28/08
9
IS42S16100
COMMANDS (cont.) No-Operation Command
CLK CKE CS RAS CAS WE A0-A9 A10 A11
HIGH
Device Deselect Command
CLK CKE CS RAS CAS WE A0-A9 A10 A11
HIGH
Mode Register Set Command
CLK CKE HIGH CS RAS CAS WE A0-A9 A10 A11
OP-CODE
Auto-Refresh Command
CLK CKE HIGH CS RAS CAS WE A0-A9 A10 A11
OP-CODE
OP-CODE
Don't Care
10
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Rev. D 01/28/08
IS42S16100
COMMANDS (cont.) Self-Refresh Command
CLK CKE CS RAS CAS WE A0-A9 A10 A11
Power Down Command
CLK CKE CS RAS CAS WE A0-A9 A10 A11
NOP
ALL BANKS IDLE
NOP NOP
NOP
Clock Suspend Command
CLK CKE CS RAS CAS WE A0-A9 A10 A11
NOP
BANK(S) ACTIVE
Burst Stop Command
CLK CKE
HIGH
NOP NOP
CS RAS CAS WE A0-A9 A10 A11
NOP
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Rev. D 01/28/08
11
IS42S16100
Mode Register Set Command
(CS, RAS, CAS, WE = LOW) The IS42S16100 product incorporates a register that defines the device operating mode. This command functions as a data input pin that loads this register from the pins A0 to A11. When power is first applied, the stipulated power-on sequence should be executed and then the IS42S16100 should be initialized by executing a mode register set command. Note that the mode register set command can be executed only when both banks are in the idle state (i.e. deactivated). Another command cannot be executed after a mode register set command until after the passage of the period tmcd, which is the period required for mode register set command execution. When the A10 pin is HIGH, this command functions as a read with auto-precharge command. After the burst read completes, the bank selected by pin A11 is precharged. When the A10 pin is LOW, the bank selected by the A11 pin remains in the activated state after the burst read completes.
Write Command
(CS, CAS, WE = LOW, RAS = HIGH) When burst write mode has been selected with the mode register set command, this command selects the bank specified by the A11 pin and starts a burst write operation at the start address specified by pins A0 to A9. This first data must be input to the DQ pins in the cycle in which this command. The selected bank must be activated before executing this command. When A10 pin is HIGH, this command functions as a write with auto-precharge command. After the burst write completes, the bank selected by pin A11 is precharged. When the A10 pin is low, the bank selected by the A11 pin remains in the activated state after the burst write completes. After the input of the last burst write data, the application must wait for the write recovery period (tdpl, tdal) to elapse according to CAS latency.
Active Command
(CS, RAS = LOW, CAS, WE= HIGH) The IS42S16100 includes two banks of 2048 rows each. This command selects one of the two banks according to the A11 pin and activates the row selected by the pins A0 to A10. This command corresponds to the fall of the RAS signal from HIGH to LOW in conventional DRAMs.
Precharge Command
(CS, RAS, WE = LOW, CAS = HIGH) This command starts precharging the bank selected by pins A10 and A11. When A10 is HIGH, both banks are precharged at the same time. When A10 is LOW, the bank selected by A11 is precharged. After executing this command, the next command for the selected bank(s) is executed after passage of the period trp, which is the period required for bank precharging. This command corresponds to the RAS signal from LOW to HIGH in conventional DRAMs
Auto-Refresh Command
(CS, RAS, CAS = LOW, WE, CKE = HIGH) This command executes the auto-refresh operation. The row address and bank to be refreshed are automatically generated during this operation. Both banks must be placed in the idle state before executing this command. The stipulated period (trc) is required for a single refresh operation, and no other commands can be executed during this period. The device goes to the idle state after the internal refresh operation completes. This command must be executed at least 2048 times every 32 ms. This command corresponds to CBR auto-refresh in conventional DRAMs.
Read Command
(CS, CAS = LOW, RAS, WE = HIGH) This command selects the bank specified by the A11 pin and starts a burst read operation at the start address specified by pins A0 to A9. Data is output following CAS latency. The selected bank must be activated before executing this command. 12
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Rev. D 01/28/08
IS42S16100
Self-Refresh Command
(CS, RAS, CAS, CKE = LOW, WE = HIGH) This command executes the self-refresh operation. The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation. The self-refresh operation is started by dropping the CKE pin from HIGH to LOW. The self-refresh operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins. The self-refresh operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed until the device internal recovery period (trc) has elapsed. After the self-refresh, since it is impossible to determine the address of the last row to be refreshed, an auto-refresh should immediately be performed for all addresses (4096 cycles). Both banks must be placed in the idle state before executing this command.
Power-Down Command
(CKE = LOW) When both banks are in the idle (inactive) state, or when at least one of the banks is not in the idle (inactive) state, this command can be used to suppress device power dissipation by reducing device internal operations to the absolute minimum. Power-down mode is started by dropping the CKE pin from HIGH to LOW. Power-down mode continues as long as the CKE pin is held low. All pins other than the CKE pin are invalid and none of the other commands can be executed in this mode. The power-down operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed until the recovery period (tcka) has elapsed. Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tref). Thus the maximum time that power-down mode can be held is just under the refresh cycle time.
Burst Stop Command
(CS, WE, = LOW, RAS, CAS = HIGH) The command forcibly terminates burst read and write operations. When this command is executed during a burst read operation, data output stops after the CAS latency period has elapsed.
Clock Suspend
(CKE = LOW) This command can be used to stop the device internal clock temporarily during a read or write cycle. Clock suspend mode is started by dropping the CKE pin from HIGH to LOW. Clock suspend mode continues as long as the CKE pin is held LOW. All input pins other than the CKE pin are invalid and none of the other commands can be executed in this mode. Also note that the device internal state is maintained. Clock suspend mode is terminated by raising the CKE pin from LOW to HIGH, at which point device operation restarts. The next command cannot be executed until the recovery period (tcka) has elapsed. Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tref). Thus the maximum time that clock suspend mode can be held is just under the refresh cycle time.
No Operation
(CS, = LOW, RAS, CAS, WE = HIGH) This command has no effect on the device.
Device Deselect Command
(CS = HIGH) This command does not select the device for an object of operation. In other words, it performs no operation with respect to the device.
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IS42S16100
COMMAND TRUTH TABLE(1,2)
Symbol Command MRS Mode Register Set(3,4) REF Auto-Refresh(5) SREF Self-Refresh(5,6) PRE Precharge Selected Bank PALL Precharge Both Banks ACT Bank Activate(7) WRIT Write WRITA Write With Auto-Precharge(8) READ Read(8) READA Read With Auto-Precharge(8) BST Burst Stop(9) NOP No Operation DESL Device Deselect SBY Clock Suspend / Standby Mode ENB Data Write / Output Enable MASK Data Mask / Output Disable CKE n-1 n H X H H H L H X H X H X H X H X H X H X H X H X H X L X H X H X CS RAS CAS WE DQM L L L L X L L L H X L L L H X L L H L X L L H L X L L H H X L H L L X L H L L X L H L H X L H L H X L H H L X L H H H X H X X X X X X X X X X X X X L X X X X H A11 A10 A9-A0 I/On OP CODE X X X X HIGH-Z X X X HIGH-Z BS L X X X H X X BS Row Row X BS L Column(18) X BS H Column(18) X BS L Column(18) X BS H Column(18) X X X X X X X X X X X X X X X X X X X X Active X X X HIGH-Z
DQM TRUTH TABLE(1,2)
Symbol ENB MASK ENBU ENBL MASKU MASKL Command Data Write / Output Enable Data Mask / Output Disable Upper Byte Data Write / Output Enable Lower Byte Data Write / Output Enable Upper Byte Data Mask / Output Disable Lower Byte Data Mask / Output Disable n-1 H H H H H H CKE n X X X X X X DQM UPPER LOWER L L H H L X X L H X X H
CKE TRUTH TABLE(1,2)
Symbol SPND -- -- REF SELF SELFX PDWN -- 14 Command Start Clock Suspend Mode Clock Suspend Terminate Clock Suspend Mode Auto-Refresh Start Self-Refresh Mode Terminate Self-Refresh Mode Start Power-Down Mode Terminate Power-Down Mode Current State Active Other States Clock Suspend Idle Idle Self-Refresh Idle Power-Down CKE n-1 n H L L L L H H H H L L H L H H L H L L H CS RAS CAS WE A11 A10 A9-A0 X X X X X X X X X X X X X X X X X X X X X L L L H X X X L L L H X X X L H H H X X X H X X X X X X L H H H X X X H X X X X X X X X X X X X X
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
OPERATION COMMAND TABLE(1,2)
Current State Command Idle DESL NOP BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Active DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Read DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Write DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Read With DESL AutoNOP Precharge BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Operation CS RAS CAS WE A11 A10 A9-A0 (12) No Operation or Power-Down H X X X X X X (12) No Operation or Power-Down L H H H X X X No Operation or Power-Down L H H L X X X Illegal L H L H V V V(18) Illegal L H L L V V V(18) Row Active L L H H V V V(18) No Operation L L H L V V X (13) Auto-Refresh or Self-Refresh L L L H X X X Mode Register Set L L L L OP CODE No Operation H X X X X X X No Operation L H H H X X X No Operation L H H L X X X Read Start(17) L H L H V V V(18) Write Start(17) L H L L V V V(18) (10) Illegal L L H H V V V(18) (15) Precharge L L H L V V X Illegal L L L H X X X Illegal L L L L OP CODE Burst Read Continues, Row Active When Done H X X X X X X Burst Read Continues, Row Active When Done L H H H X X X Burst Interrupted, Row Active After Interrupt L H H L X X X Burst Interrupted, Read Restart After Interrupt(16) L H L H V V V(18) (11,16) Burst Interrupted Write Start After Interrupt L H L L V V V(18) (10) Illegal L L H H V V V(18) Burst Read Interrupted, Precharge After Interrupt L L H L V V X Illegal L L L H X X X Illegal L L L L OP CODE Burst Write Continues, Write Recovery When Done H X X X X X X Burst Write Continues, Write Recovery When Done L H H H X X X Burst Write Interrupted, Row Active After Interrupt L H H L X X X Burst Write Interrupted, Read Start After Interrupt(11,16) L H L H V V V(18) Burst Write Interrupted, Write Restart After Interrupt(16) L H L L V V V(18) (10) Illegal L L H H V V V(18) Burst Write Interrupted, Precharge After Interrupt L L H L V V X Illegal L L L H X X X Illegal L L L L OP CODE Burst Read Continues, Precharge When Done H X X X X X X Burst Read Continues, Precharge When Done L H H H X X X Illegal L H H L X X X Illegal L H L H V V V(18) Illegal L H L L V V V(18) (10) Illegal L L H H V V V(18) (10) Illegal L L H L V V X Illegal L L L H X X X Illegal L L L L OP CODE 15
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Rev. D 01/28/08
IS42S16100
OPERATION COMMAND TABLE(1,2)
Current State Command Write With DESL Auto-Precharge NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Precharge DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Immediately DESL Following NOP Row Active BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
Write Recovery DESL NOP BST
Operation
CS RAS CAS WE A11 A10 A9-A0
H L X H X H X H X X X X X X
Burst Write Continues, Write Recovery And Precharge When Done Burst Write Continues, Write Recovery And Precharge
Illegal Illegal Illegal Illegal(10) Illegal(10) Illegal Illegal No Operation, Idle State After trp Has Elapsed No Operation, Idle State After trp Has Elapsed No Operation, Idle State After trp Has Elapsed Illegal(10) Illegal(10) Illegal(10)
L L L L L L L H L
L
H H H L L L L X H
H
H L L H H L L X H
H
L H L H L H L X H
L
X V V V V X
X X (18) VV V V(18) V V(18) V X X X OPCODE X X X X X X
X X X
No Operation, Idle State After trp Has Elapsed(10) Illegal Illegal No Operation, Row Active After trcd Has Elapsed No Operation, Row Active After trcd Has Elapsed No Operation, Row Active After trcd Has Elapsed Illegal(10) Illegal(10) Illegal(10,14) Illegal(10)
Illegal Illegal
L L L L L L H L L L L L L L
H H L L L L X H H H H L L L
L X H
L L H H L L X H H L L H H L
L X H
H L H L H L X H L H L H L H
L X H
V V(18) V V(18) V V(18) V X X X OP CODE X X X X X X X X X V V V(18) V V V(18) V V V(18) V V V V X V X
X X
V X
X X
L No Operation, Row Active After tdpl Has Elapsed H No Operation, Row Active After tdpl Has Elapsed L No Operation, Row Active After tdpl Has Elapsed L
OP CODE X X X X
READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
Read Start Write Restart Illegal(10) Illegal(10) Illegal Illegal
L L L L L L
H H H L L L L
H L L H H L L
L H L H L H L
X X X (18) V VV V V V(18) V V V(18) V V X X X X OP CODE
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Rev. D 01/28/08
IS42S16100
OPERATION COMMAND TABLE(1,2)
Current State Write Recovery With AutoPrecharge Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Refresh DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Mode Register DESL Set NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Operation No Operation, Idle State After tdal Has Elapsed No Operation, Idle State After tdal Has Elapsed No Operation, Idle State After tdal Has Elapsed Illegal(10) Illegal(10) Illegal(10) Illegal(10) Illegal Illegal No Operation, Idle State After trp Has Elapsed No Operation, Idle State After trp Has Elapsed No Operation, Idle State After trp Has Elapsed Illegal Illegal Illegal Illegal Illegal Illegal No Operation, Idle State After tmcd Has Elapsed No Operation, Idle State After tmcd Has Elapsed No Operation, Idle State After tmcd Has Elapsed Illegal Illegal Illegal Illegal Illegal Illegal CS RAS CAS WE A11 A10 A9-A0 H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OP CODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OP CODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OP CODE
Notes: 1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input 2. All input signals are latched on the rising edge of the CLK signal. 3. Both banks must be placed in the inactive (idle) state in advance. 4. The state of the A0 to A11 pins is loaded into the mode register as an OP code. 5. The row address is generated automatically internally at this time. The DQ pin and the address pin data is ignored. 6. During a self-refresh operation, all pin data (states) other than CKE is ignored. 7. The selected bank must be placed in the inactive (idle) state in advance. 8. The selected bank must be placed in the active state in advance. 9. This command is valid only when the burst length set to full page. 10. This is possible depending on the state of the bank selected by the A11 pin. 11. Time to switch internal busses is required. 12. The IS42S16100 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle state. Input pins other than CKE are ignored at this time. 13. The IS42S16100 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state. Input pins other than CKE are ignored at this time. 14. Possible if trrd is satisfied. 15. Illegal if tras is not satisfied. 16. The conditions for burst interruption must be observed. Also note that the IS42S16100 will enter the pre charged state immediately after the burst operation completes if auto-precharge is selected. 17. Command input becomes possible after the period trcd has elapsed. Also note that the IS42S16100 will enter the precharged state immediately after the burst operation completes if auto-precharge is selected. 18. A8,A9 = don't care.
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IS42S16100
CKE RELATED COMMAND TRUTH TABLE(1)
Current State Self-Refresh
Self-Refresh Recovery
Power-Down
Both Banks Idle
Other States
CKE Operation n-1 n Undefined H X Self-Refresh Recovery(2) L H Self-Refresh Recovery(2) L H (2) Illegal L H Illegal(2) L H Self-Refresh L L Idle State After trc Has Elapsed H H Idle State After trc Has Elapsed H H Illegal H H Illegal H H Power-Down on the Next Cycle H L Power-Down on the Next Cycle H L Illegal H L Illegal H L Clock Suspend Termination on the Next Cycle (2) L H Clock Suspend L L Undefined H X Power-Down Mode Termination, Idle After L H That Termination(2) Power-Down Mode L L No Operation H H See the Operation Command Table H H Bank Active Or Precharge H H Auto-Refresh H H Mode Register Set H H See the Operation Command Table H L See the Operation Command Table H L See the Operation Command Table H L Self-Refresh(3) H L See the Operation Command Table H L Power-Down Mode(3) L X See the Operation Command Table H H Clock Suspend on the Next Cycle(4) H L Clock Suspend Termination on the Next Cycle L H Clock Suspend Termination on the Next CycleL L
CS X H L L L X H L L L H L L L X X X X X H L L L L H L L L L X X X X X
RAS CAS WE X X X X X X H H X H L X L X X X X X X X X H H X H L X L X X X X X H H X H L X L X X X X X X X X X X X X X X X X H L L L X H L L L X X X X X X X X H L L X X H L L X X X X X X X X X H L X X X H L X X X X X
A11 A10 A9-A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X OP CODE X X X X X X X X X X X X OP CODE X X X X X X X X X X X X X X X X X X X X
Notes: 1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input 2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH. The minimum setup time (tcka) required before all commands other than mode termination must be satisfied. 3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode. 4. The input must be command defined in the operation command table.
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Rev. D 01/28/08
IS42S16100
TWO BANKS OPERATION COMMAND TRUTH TABLE(1,2)
Operation DESL NOP BST CS RAS CAS WE A11 A10 A9-A0 H X X X X X X L H H H X X X L H H L X X X
READ/READA
L
H
L
H
WRIT/WRITA
L
H
L
L
ACT PRE/PALL
L L
L L
H H
H L
REF MRS
L L
L L
L L
H L
H H CA(3) H H CA(3) H L CA(3) H L CA(3) L H CA(3) L H CA(3) L L CA(3) L L CA(3) H H CA(3) H H CA(3) H L CA(3) H L CA(3) L H CA(3) L H CA(3) L L CA(3) L L CA(3) H RA RA L RA RA X H X X H X H L X H L X L L X L L X X X X OPCODE
Previous State Next State BANK 0BANK 1 BANK 0BANK 1 Any Any Any Any Any Any Any Any R/W/A I/A A I/A I I/A I I/A I/A R/W/A I/A A I/A I I/A I I/A R/W/A I/A RP R/W A A RP I/A R/W/A I/A R R/W A A R R/W/A I/A RP I/A A R/W RP A R/W/A I/A R I/A A R/W R A I/A R/W/A I/A WP R/W A A WP I/A R/W/A I/A W R/W A A W R/W/A I/A WP I/A A R/W WP A R/W/A I/A W I/A A R/W W A Any I Any A I Any A Any R/W/A/I I/A I I I/A R/W/A/I I I I/A R/W/A/I I/A I R/W/A/I I/A R/W/A/I I R/W/A/I I/A I I/A I/A R/W/A/I I R/W/A/I I I I I I I I I
Notes: 1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address 2. The device state symbols are interpreted as follows: I Idle (inactive state) A Row Active State R Read W Write RP Read With Auto-Precharge WP Write With Auto-Precharge Any Any State 3. CA: A8,A9 = don't care.
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Rev. D 01/28/08
19
IS42S16100
SIMPLIFIED STATE TRANSITION DIAGRAM (One Bank Operation)
SELF REFRESH
SREF entry SREF exit
MODE REGISTER SET
MRS
IDLE
REF
AUTO REFRESH
CKE_ CKE ACT
IDLE POWER DOWN
ACTIVE POWER DOWN
CKE_ CKE
BST
BANK ACTIVE
WRIT READ
BST
WRIT WRITA READ CKE_ CKE WRITA CKE_ CKE WRITA READA READA
READ
WRITE
WRIT
READ
CKE_
CLOCK SUSPEND
READA CKE_
CKE
CLOCK SUSPEND
WRITE WITH AUTO PRECHARGE
PRE
PRE PRE
READ WITH AUTO PRECHARGE
CKE
POWER APPLIED
POWER ON
PRE
PRECHARGE
Automatic transition following the completion of command execution. Transition due to command input.
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Rev. D 01/28/08
IS42S16100
Device Initialization At Power-On
(Power-On Sequence) As is the case with conventional DRAMs, the IS42S16100 product must be initialized by executing a stipulated poweron sequence after power is applied. After power is applied and Vdd and VddQ reach their stipulated voltages, set and hold the CKE and DQM pins HIGH for 100 s. Then, execute the precharge command to precharge both bank. Next, execute the auto-refresh command twice or more and define the device operation mode by executing a mode register set command. The mode register set command can be also set before auto-refresh command.
Burst Length
When writing or reading, data can be input or output data continuously. In these operations, an address is input only once and that address is taken as the starting address internally by the device. The device then automatically generates the following address. The burst length field in the mode register stipulates the number of data items input or output in sequence. In the IS42S16100 product, a burst length of 1, 2, 4, 8, or full page can be specified. See the table on the next page for details on setting the mode register.
Burst Type
The burst data order during a read or write operation is stipulated by the burst type, which can be set by the mode register set command. The IS42S16100 product supports sequential mode and interleaved mode burst type settings. See the table on the next page for details on setting the mode register. See the "Burst Length and Column Address Sequence" item for details on DQ data orders in these modes.
Mode Register Settings
The mode register set command sets the mode register. When this command is executed, pins A0 to A9, A10, and A11 function as data input pins for setting the register, and this data becomes the device internal OP code. This OP code has four fields as listed in the table below. Input Pin A11, A10, A9, A8, A7 A6, A5, A4 A3 A2, A1, A0 Field Mode Options CAS Latency Burst Type Burst Length
Write Mode
Burst write or single write mode is selected by the OP code (A11, A10, A9) of the mode register. A burst write operation is enabled by setting the OP code (A11, A10, A9) to (0,0,0). A burst write starts on the same cycle as a write command set. The write start address is specified by the column address and bank select address at the write command set cycle. A single write operation is enabled by setting OP code (A11, A10, A9) to (0, 0,1). In a single write operation, data is only written to the column address and bank select address specified by the write command set cycle without regard to the bust length setting.
Note that the mode register set command can be executed only when both banks are in the idle (inactive) state. Wait at least two cycles after executing a mode register set command before executing the next command.
CAS Latency
During a read operation, the between the execution of the read command and data output is stipulated as the CAS latency. This period can be set using the mode register set command. The optimal CAS latency is determined by the clock frequency and device speed grade. See the "Operating Frequency / Latency Relationships" item for details on the relationship between the clock frequency and the CAS latency. See the table on the next page for details on setting the mode register.
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IS42S16100
MODE REGISTER
A11 A10 A9 WRITE MODE A8 A7 A6 LT MODE A5 A4 BT A3 A2 BL A1 A0
Address Bus (Ax) Mode Register (Mx)
M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 Sequential Interleaved 1 1 2 2 4 4 8 8 Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
M2 Burst Length 0 0 0 0 1 1 1 1
Burst Type
M3 0 1
Type Sequential Interleaved
M6 Latency Mode 0 0 0 0 1 1 1 1
M5 0 0 1 1 0 0 1 1
M4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
M11 0 0
M10 0 0
M9 1 0
M8 0 0
M7 0 0
Write Mode Burst Read & Single Write Burst Read & Burst Write
Note: Other values for these bits are reserved.
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Rev. D 01/28/08
IS42S16100
BURST LENGTH AND COLUMN ADDRESS SEQUENCE Burst Length
2 4
Column Address A2 A1 A0
X X X X X X 0 0 0 0 1 1 1 1 n X X 0 0 1 1 0 0 1 1 0 0 1 1 n 0 1 0 1 0 1 0 1 0 1 0 1 0 1 n
Address Sequence Sequential Interleaved
0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 Cn+3, Cn+4..... ...Cn-1(Cn+255), Cn(Cn+256)..... 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 None
8
Full Page (256)
Notes: 1. The burst length in full page mode is 256.
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Rev. D 01/28/08
23
IS42S16100
BANK SELECT AND PRECHARGE ADDRESS ALLOCATION
Row X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 Command) X11 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 -- -- -- -- -- -- -- -- -- -- 0 1 0 1 -- -- -- -- -- -- -- -- -- -- 0 1 0 1 Row Address Row Address Row Address Row Address Row Address Row Address Row Address Row Address Row Address Row Address Precharge of the Selected Bank (Precharge Command) Precharge of Both Banks (Precharge Command) Bank 0 Selected (Precharge and Active Command) Bank 1 Selected (Precharge and Active Command) Column Address Column Address Column Address Column Address Column Address Column Address Column Address Column Address Don't Care Don't Care Auto-Precharge - Disabled Auto-Precharge - Enables Bank 0 Selected (Read and Write Commands) Bank 1 Selected (Read and Write Commands) Row Address (Active
Column
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Rev. D 01/28/08
IS42S16100
Burst Read
The read cycle is started by executing the read command. The address provided during read command execution is used as the starting address. First, the data corresponding to this address is output in synchronization with the clock signal after the CAS latency period. Next, data corresponding to an address generated automatically by the device is output in synchronization with the clock signal. The output buffers go to the LOW impedance state CAS latency minus one cycle after the read command, and go to the HIGH impedance state automatically after the last data is output. However, the case where the burst length is a full page is an exception. In this case the output buffers must be set to the high impedance state by executing a burst stop command. Note that upper byte and lower byte output data can be masked independently under control of the signals applied to the U/LDQM pins. The delay period (tqmd) is fixed at two, regardless of the CAS latency setting, when this function is used. The selected bank must be set to the active state before executing this command.
CLK COMMAND UDQM LDQM DQ8-DQ15 DQ0-DQ 7
READ (CA=A, BANK 0)
READ A0 tQMD=2
DOUT A0 DOUT A0
HI-Z
DOUT A2
DOUT A3
HI-Z
DOUT A1
HI-Z
DATA MASK (LOWER BYTE)
CAS latency = 3, burst length = 4
DATA MASK (UPPER BYTE)
Burst Write
The write cycle is started by executing the command. The address provided during write command execution is used as the starting address, and at the same time, data for this address is input in synchronization with the clock signal. Next, data is input in other in synchronization with the clock signal. During this operation, data is written to address generated automatically by the device. This cycle terminates automatically after a number of clock cycles determined by the stipulated burst length. However, the case where the burst length is a full page is an exception. In this case the write cycle must be terminated by executing
CLK
a burst stop command. The latency for DQ pin data input is zero, regardless of the CAS latency setting. However, a wait period (write recovery: tdpl) after the last data input is required for the device to complete the write operation. Note that the upper byte and lower byte input data can be masked independently under control of the signals applied to the U/LDQM pins. The delay period (tdmd) is fixed at zero, regardless of the CAS latency setting, when this function is used. The selected bank must be set to the active state before executing this command.
COMMAND DQ
WRITE DIN 0 DIN 1 DIN 2 DIN 3
BURST LENGTH
CAS latency = 2,3, burst length = 4 Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
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IS42S16100
Read With Auto-Precharge
The read with auto-precharge command first executes a burst read operation and then puts the selected bank in the precharged state automatically. After the precharge completes, the bank goes to the idle state. Thus this command performs a read command and a precharge command in a single operation. During this operation, the delay period (tpql) between the last burst data output and the start of the precharge operation differs depending on the CAS latency setting. When the CAS latency setting is two, the precharge operation starts on one clock cycle before the last burst data is output (tpql = -1). When the CAS latency setting is three, the precharge operation starts on two clock cycles before the last burst data is output (tpql = -2). Therefore, the selected bank can be made active after a delay of trp from the start position of this precharge operation. The selected bank must be set to the active state before executing this command. The auto-precharge function is invalid if the burst length is set to full page. CAS Latency tpql 3 -2 2 -1
CLK COMMAND DQ
READ WITH AUTO-PRECHARGE (BANK 0)
READA 0 tPQL DOUT 0 DOUT 1 DOUT 2 DOUT 3 tRP
ACT 0
PRECHARGE START
CAS latency = 2, burstlength = 4
CLK COMMAND DQ
READ WITH AUTO-PRECHARGE (BANK 0)
READA 0 tPQL DOUT 0
PRECHARGE START
ACT 0
DOUT 1
DOUT 2 tRP
DOUT 3
CAS latency = 3, burstlength = 4
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IS42S16100
Write With Auto-Precharge
The write with auto-precharge command first executes a burst write operation and then puts the selected bank in the precharged state automatically. After the precharge completes the bank goes to the idle state. Thus this command performs a write command and a precharge command in a single operation. During this operation, the delay period (tdal) between the last burst data input and the completion of the precharge operation differs depending on the CAS latency setting. The delay (tdal) is trp plus one CLK period. That is, the precharge operation starts one clock period after the last burst data input. Therefore, the selected bank can be made active after a delay of tdal. The selected bank must be set to the active state before executing this command. The auto-precharge function is invalid if the burst length is set to full page. CAS Latency tdal 3 2CLK +trp 2 2CLK +trp
CLK COMMAND DQ
WRITE A0 DIN 0 DIN 1 DIN 2 DIN 3 tRP tDAL
ACT 0
PRECHARGE START
WRITE WITH AUTO-PRECHARGE (BANK 0)
CAS latency = 2, burstlength = 4
CLK COMMAND DQ
WRITE A0
PRECHARGE START
ACT 0 DIN 1 DIN 2 DIN 3 tRP tDAL
DIN 0
WRITE WITH AUTO-PRECHARGE (BANK 0)
CAS latency = 3, burstlength = 4
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IS42S16100
Interval Between Read Command
A new command can be executed while a read cycle is in progress, i.e., before that cycle completes. When the second read command is executed, after the CAS latency has elapsed, data corresponding to the new read command is output in place of the data due to the previous read command. The interval between two read command (tccd) must be at least one clock cycle. The selected bank must be set to the active state before executing this command.
CLK COMMAND DQ
tCCD
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
READ A0
READ B0 DOUT A0 DOUT B0 DOUT B1 DOUT B3
DOUT B2
CAS latency = 2, burstlength = 4
Interval Between Write Command
A new command can be executed while a write cycle is in progress, i.e., before that cycle completes. At the point the second write command is executed, data corresponding to the new write command can be input in place of the data for the previous write command. The interval between two write commands (tccd) must be at least one clock cycle. The selected bank must be set to the active state before executing this command.
CLK
tCCD
COMMAND DQ
WRITE A0 DIN A0
WRITE B0 DIN B0 DIN B1 DIN B2 DIN B3
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CAS latency = 3, burstlength = 4
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Rev. D 01/28/08
IS42S16100
Interval Between Write and Read Commands
A new read command can be executed while a write cycle is in progress, i.e., before that cycle completes. Data corresponding to the new read command is output after the CAS latency has elapsed from the point the new read command was executed. The I/On pins must be placed in the HIGH impedance state at least one cycle before data is output during this operation. The interval (tccd) between command must be at least one clock cycle. The selected bank must be set to the active state before executing this command.
CLK
tCCD
COMMAND DQ
WRITE A0 DIN A0
READ B0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
HI-Z
WRITE (CA=A, BANK 0)
READ (CA=B, BANK 0)
CAS latency = 2, burstlength = 4
CLK
tCCD
COMMAND DQ
WRITE A0 DIN A0
READ B0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
HI-Z
READ (CA=B, BANK 0)
WRITE (CA=A, BANK 0)
CAS latency = 3, burstlength = 4
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29
IS42S16100
Interval Between Read and Write Commands
A read command can be interrupted and a new write command executed while the read cycle is in progress, i.e., before that cycle completes. Data corresponding to the new write command can be input at the point new write command is executed. To prevent collision between input and output data at the DQn pins during this operation, the output data must be masked using the U/LDQM pins. The interval (tccd) between these commands must be at least one clock cycle. The selected bank must be set to the active state before executing this command.
CLK
tCCD
COMMAND U/LDQM DQ
READ A0
WRITE B0
HI-Z
DIN B0
DIN B1
DIN B2
DIN B3
READ (CA=A, BANK 0)
WRITE (CA=B, BANK 0)
CAS latency = 2, 3, burstlength = 4
30
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Precharge
The precharge command sets the bank selected by pin A11 to the precharged state. This command can be executed at a time tras following the execution of an active command to the same bank. The selected bank goes to the idle state at a time trp following the execution of the precharge command, and an active command can be executed again for that bank. If pin A10 is low when this command is executed, the bank selected by pin A11 will be precharged, and if pin A10 is HIGH, both banks will be precharged at the same time. This input to pin A11 is ignored in the latter case.
Read Cycle Interruption Using the Precharge Command
A read cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (trql) from the execution of the precharge command to the completion of the burst output is the clock cycle of CAS latency. CAS Latency trql 3 3 2 2
CLK
tRQL
COMMAND DQ
READ A0
PRE 0
DOUT A0 DOUT A1 DOUT A2
READ (CA=A, BANK 0) PRECHARGE (BANK 0)
HI-Z
CAS latency = 2, burstlength = 4
CLK
tRQL
COMMAND DQ
READ A0
PRE 0
DOUT A0 DOUT A1 DOUT A2
READ (CA=A, BANK 0) PRECHARGE (BANK 0)
HI-Z
CAS latency = 3, burstlength = 4
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Rev. D 01/28/08
31
IS42S16100
Write Cycle Interruption Using the Precharge Command
A write cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (twdl) from the precharge command to the point where burst input is invalid, i.e., the point where input data is no longer written to device internal memory is zero clock cycles regardless of the CAS. To inhibit invalid write, the DQM signal must be asserted HIGH with the precharge command. This precharge command and burst write command must be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual bank operation. Inversely, to write all the burst data to the device, the precharge command must be executed after the write data recovery period (tdpl) has elapsed. Therefore, the precharge command must be executed on one clock cycle that follows the input of the last burst data item. CAS Latency twdl tdpl 3 0 1 2 0 1
CLK
tWDL=0
COMMAND DQM DQ
WRITE A0
PRE 0
DIN A0
DIN A1
DIN A2
DIN A3
MASKED BY DQM
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS latency = 2, burstlength = 4
CLK
tDPL
COMMAND DQ
WRITE A0
PRE 0
DIN A0
DIN A1
DIN A2
DIN A3
PRECHARGE (BANK 0)
WRITE (CA=A, BANK 0)
CAS latency = 3, burstlength = 4
32
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Read Cycle (Full Page) Interruption Using the Burst Stop Command
The IS42S16100 can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full page. The IS42S16100 repeats the operation starting at the 256th cycle with the data output returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle. A precharge command must be executed within the ACT to PRE command period (tras max.) following the burst stop command. After the period (trbd) required for burst data output to stop following the execution of the burst stop command has elapsed, the outputs go to the HIGH impedance state. This period (trbd) is two clock cycle when the CAS latency is two and three clock cycle when the CAS latency is three. CAS Latency trbd 3 3 2 2
CLK
tRBD
COMMAND DQ
READ A0
BST
DOUT A0 DOUT A0
READ (CA=A, BANK 0)
DOUT A1
DOUT A2
BURST STOP
DOUT A3
HI-Z
CAS latency = 2, burstlength = 4
CLK
tRBD
COMMAND DQ
READ A0
BST
DOUT A0 DOUT A0
READ (CA=A, BANK 0)
DOUT A1
BURST STOP
DOUT A2
DOUT A3
HI-Z
CAS latency = 3, burstlength = 4
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Rev. D 01/28/08
33
IS42S16100
Write Cycle (Full Page) Interruption Using the Burst Stop Command
The IS42S16100 can input data continuously from the burst start address (a) to location a+255 during a write cycle in which the burst length is set to full page. The IS42S16100 repeats the operation starting at the 256th cycle with data input returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle. A precharge command
must be executed within the ACT to PRE command period (tras max.) following the burst stop command. After the period (twbd) required for burst data input to stop following the execution of the burst stop command has elapsed, the write cycle terminates. This period (twbd) is zero clock cycles, regardless of the CAS latency.
CLK
tWBD=0 tRP
PRE 0
COMMAND DQ
WRITE A0
BST
INVALID DATA
DIN A0
DIN A1
DIN A
DIN A1
DIN A2
BURST STOP PRECHARGE (BANK 0)
READ (CA=A, BANK 0)
Don't Care
Burst Data Interruption Using the U/LDQM Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked) during a read cycle using the U/LDQM pins. Regardless of the CAS latency, two clock cycles (tqmd) after one of the U/LDQM pins goes HIGH, the corresponding outputs go to the HIGH impedance state. Subsequently, the outputs are maintained in the high impedance state as long as that U/LDQM pin remains HIGH. When the U/LDQM pin goes LOW, output is resumed at a time tqmd later. This
output control operates independently on a byte basis with the UDQM pin controlling upper byte output (pins DQ8-DQ15) and the LDQM pin controlling lower byte output (pins DQ0 to DQ7). Since the U/LDQM pins control the device output buffers only, the read cycle continues internally and, in particular, incrementing of the internal burst counter continues.
CLK COMMAND UDQM LDQM DQ8-DQ15 DQ0-DQ 7
READ (CA=A, BANK 0)
READ A0 tQMD=2
DOUT A0 DOUT A0
HI-Z
DOUT A2
DOUT A3
HI-Z
DOUT A1
HI-Z
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
CAS latency = 2, burstlength = 4 34 Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Burst Data Interruption U/LDQM Pins (Write Cycle)
Burst data input can be temporarily interrupted (muted ) during a write cycle using the U/LDQM pins. Regardless of the CAS latency, as soon as one of the U/LDQM pins goes HIGH, the corresponding externally applied input data will no longer be written to the device internal circuits. Subsequently, the corresponding input continues to be muted as long as that U/LDQM pin remains HIGH. The IS42S16100 will revert to accepting input as soon as
CLK COMMAND UDQM
tDMD=0 WRITE A0
that pin is dropped to LOW and data will be written to the device. This input control operates independently on a byte basis with the UDQM pin controlling upper byte input (pin DQ8 to DQ15) and the LDQM pin controlling the lower byte input (pins DQ0 to DQ7). Since the U/LDQM pins control the device input buffers only, the cycle continues internally and, in particular, incrementing of the internal burst counter continues.
LDQM DQ8-DQ15 DQ0-DQ7
WRITE (CA=A, BANK 0)
DIN A1 DIN A0
DATA MASK (LOWER BYTE)
DIN A2
DIN A3 DIN A3
DATA MASK (UPPER BYTE)
Don't Care
CAS latency = 2, burstlength = 4
Burst Read and Single Write
The burst read and single write mode is set up using the mode register set command. During this operation, the burst read cycle operates normally, but the write cycle only writes a single data item for each write cycle. The CAS latency and DQM latency are the same as in normal mode.
CLK COMMAND DQ
WRITE A0
DIN A0
WRITE (CA=A, BANK 0)
CAS latency = 2, 3 Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
35
IS42S16100
Bank Active Command Interval
When the selected bank is precharged, the period trp has elapsed and the bank has entered the idle state, the bank can be activated by executing the active command. If the other bank is in the idle state at that time, the active command can be executed for that bank after the period trrd has elapsed. At that point both banks will be in the active state. When a bank active command has been executed, a precharge command must be executed for
that bank within the ACT to PRE command period (tras max). Also note that a precharge command cannot be executed for an active bank before tras (min) has elapsed. After a bank active command has been executed and the trcd period has elapsed, read write (including autoprecharge) commands can be executed for that bank.
CLK
tRRD
COMMAND
ACT 0
ACT 1
BANK ACTIVE (BANK 1)
BANK ACTIVE (BANK 0)
CLK
tRCD
COMMAND
ACT 0
READ 0
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 0)
CAS latency = 3
Clock Suspend
When the CKE pin is dropped from HIGH to LOW during a read or write cycle, the IS42S16100 enters clock suspend mode on the next CLK rising edge. This command reduces the device power dissipation by stopping the device internal clock. Clock suspend mode continues as long as the CKE pin remains low. In this state, all inputs other than CKE pin are invalid and no other commands can be executed. Also, the device internal states are maintained. When the CKE pin goes from LOW to HIGH clock suspend mode is terminated on the next CLK rising edge and device operation resumes. The next command cannot be executed until the recovery period (tcka) has elapsed. Since this command differs from the self-refresh command described previously in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tref). Thus the maximum time that clock suspend mode can be held is just under the refresh cycle time.
CLK
CKE COMMAND DQ
READ (BANK 0)
READ 0 DOUT 0 DOUT 1 DOUT 2 DOUT 3
CLOCK SUSPEND
CAS latency = 2, burstlength = 4 36 Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
OPERATION TIMING EXAMPLE Power-On Sequence, Mode Register Set Cycle
T0 CLK
tCK
T1
tCHI
T2
T3
T10
T17
T18
T19
T20
tCL
CKE HIGH
tCS
tCH tCS tCH tCH tCH tAS tAH CODE tAS tAH
BANK 0 & 1
CS RAS
tCS
CAS
tCS
WE A0-A9
tAS CODE tAS tAH CODE BANK 0 ROW tAH ROW BANK 1
A10 A11 DQM HIGH DQ
WAIT TIME T=100 s
tRP
tRC
tRC
tMCD
tRAS tRC
Undefined
CAS latency = 2, 3
Don't Care
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Rev. D 01/28/08
37
IS42S16100
Power-Down Mode Cycle
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
Tn
Tn+1
tCKH tCKA
Tn+2
Tn+3
tCL
tCKS
CKE
tCS
CS
tCH tCH tCH tAS tAH ROW tAS tAH
BANK 0 & 1 BANK 0 OR 1
RAS
tCS
CAS
tCS
WE A0-A9 A10 A11 DQM DQ
tRP 
   POWER DOWN MODE EXIT POWER DOWN MODE  tRAS tRC
ROW BANK 1 BANK 0
BANK 1 BANK 0
Undefined
CAS latency = 2, 3
Don't Care
38
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Rev. D 01/28/08
IS42S16100
Auto-Refresh Cycle
T0 CLK
tCKS tCK tCH tCS tCH tCH tCH tCHI tCL
T1
T2
T3
Tl
Tm
Tn
Tn+1
CKE
tCS
CS RAS
tCS
CAS
tCS
WE A0-A9
tAS tAH
BANK 0 & 1
ROW ROW BANK 1
A10 A11
BANK 0
DQM DQ
tRP   tRC  tRC  tRC  tRAS tRC
Undefined
CAS latency = 2, 3
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
39
IS42S16100
Self-Refresh Cycle
T0
T1 tCHI
T2
T3
Tm
Tm+1
Tm+2
Tn
CLK
tCKS tCK tCKA tCS tCH tCS tCH tCH tCH tCKA tCL tCKS tCKS
CKE CS RAS
tCS
CAS
tCS
WE A0-A9
tAS tAH
BANK 0 & 1
A10 A11 DQM DQ
tRP  
SELF REFRESH MODE
EXIT SELF REFRESH
tRC 
tRC
Undefined
CAS latency = 2, 3 Note 1: A8,A9 = Don't Care.
Don't Care
40
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Rev. D 01/28/08
IS42S16100
Read Cycle
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tQMD tAC tAC tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN m BANK 0 AND 1 NO PRE BANK 1 BANK 0 OR 1 BANK 1 tCH BANK 0 tAC tOH
DOUT m+1
ROW ROW BANK 1 BANK 0
tAC tOH
DOUT m+2
tOH
DOUT m+3
DQ
tRCD tRAS tRC   tLZ tCAC
tRQL tRP 
 
tHZ
tRCD tRAS tRC 
Undefined
CAS latency = 2, burstlength = 4 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
41
IS42S16100
Read Cycle / Auto-Precharge
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tQMD tAC tAC tOH
DOUT m (1)
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 DQM
COLUMN m AUTO PRE BANK 1 tCH tAC tOH
DOUT m+1
ROW ROW BANK 1 BANK 0
tAC tOH
DOUT m+2
tOH
DOUT m+3
DQ
tLZ tRCD tRAS tRC   tCAC
tPQL tRP
tHZ
tRCD tRAS tRC 
Undefined
CAS latency = 2, burstlength = 4 Note 1: A8,A9 = Don't Care.
Don't Care
42
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Rev. D 01/28/08
IS42S16100
Read Cycle / Full Page
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tQMD tAC tAC tOH
DOUT 0m (1)
T1
tCHI
T2
T3
T4
T5
T6
T260
T261
T262
T263
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 DQM
COLUMN
BANK 0 OR 1 BANK 0 tCH tAC tOH
DOUT 0m+1
tAC tOH
DOUT 0m-1
tAC tOH
DOUT 0m
tOH
DOUT 0m+1
DQ
tLZ tRCD tRAS
(BANK 0) (BANK 0)
tCAC
tRBD
tHZ tRP
(BANK 0)
tRC




Undefined
CAS latency = 2, burstlength = full page Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
43
IS42S16100
Read Cycle / Ping-Pong Operation (Bank Switching)
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tQMD tAC tAC tOH tOH
DOUT 0m+1 DOUT 0m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMN AUTO PRE
ROW ROW
COLUMN AUTO PRE
ROW ROW
NO PRE BANK 1 BANK 1
BANK 0 OR 1 BANK 0 tCH tAC tAC tOH
DOUT 1m
BANK 0 OR 1 BANK 0 BANK 1
tOH
DOUT 1m+1
DQ
(BANK 0 TO 1) (BANK 0) (BANK 0) (BANK 0)
tRRD
tLZ tCAC tRCD
tHZ
(BANK 1) (BANK 1)
tLZ
tHZ
(BANK 0) (BANK 0) (BANK 0)
tRCD
(BANK 1)
tCAC
tRCD
tRAS tRC
(BANK 0)
tRP
tRAS tRC
(BANK 1) (BANK 1)
tRAS tRC
(BANK1)
tRP

 

 



Undefined
CAS latency = 2, burstlength = 2 Note 1: A8,A9 = Don't Care.
Don't Care
44
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Rev. D 01/28/08
IS42S16100
Write Cycle
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tCH NO PRE BANK 1 BANK 0 OR 1 BANK 1 BANK 0
(1)
RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 DQM
COLUMN m BANK 0 AND 1
ROW ROW BANK 1 BANK 0
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH tDS DIN m+2
tDH DIN m+3 tDPL tRP tRCD tRAS tRC 
DQ
tRCD tRAS tRC 

 
Undefined
CAS latency = 2, burstlength = 4 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
45
IS42S16100
Write Cycle / Auto-Precharge
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tCH BANK 0 AUTO PRE BANK 1 ROW BANK 1 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN m
ROW
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH tDS DIN m+2
tDH DIN m+3 tDAL tRP tRCD tRAS tRC 
DQ
tRCD tRAS tRC 

Undefined
CAS latency = 2, burstlength = 4 Note 1: A8,A9 = Don't Care.
Don't Care
46
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Rev. D 01/28/08
IS42S16100
Write Cycle / Full Page
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tCH BANK 0 OR 1 BANK 0 tCHI tCL
T1
T2
T3
T4
T5
T258
T259
T260
T261
T262
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN m
tDS
tDH tDS DIN 0m
tDH tDS DIN 0m+1
tDH tDS DIN 0m+2
tDH DIN 0m-1 DIN 0m tDPL tRP
DQ
tRCD tRAS tRC 



Undefined
CAS latency = 2, burst length = full page Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
47
IS42S16100
Write Cycle / Ping-Pong Operation
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 BANK 1 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMN AUTO PRE
ROW ROW
COLUMN AUTO PRE
ROW ROW
NO PRE BANK 1
BANK 0 OR 1 BANK 0 BANK 0 tCH
tDS
tDH tDS DIN 0m
tDH tDS DIN 0m+1
tDH tDS DIN 0m+2
tDH tDS DIN 0m+3 tDPL
tDH tDS DIN 1m
tDH tDS DIN 1m+1
tDH tDS DIN 1m+2
tDH DIN 1m+3 tDPL
DQ
(BANK 0 TO 1) (BANK 0) (BANK 0) (BANK 0)
tRRD
tRCD
(BANK 1)
tRCD
tRAS tRC
(BANK 0)
tRP
(BANK 0) (BANK 0) (BANK 0)
tRCD
tRAS tRC
(BANK 1) (BANK 1)
tRAS tRC

 

 


Undefined
CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
48
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Rev. D 01/28/08
IS42S16100
Read Cycle / Page Mode
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 tCS tQMD tAC BANK 0 tCH tAC tOH
DOUT n
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMN m
COLUMN n
COLUMN o AUTO PRE BANK 0 AND 1 BANK 0 OR 1 BANK 1 BANK 0
tAC tOH
DOUT m
tAC tOH
DOUT m+1
tAC tOH
DOUT n+1
tAC tOH
DOUT o
tOH
DOUT o+1
DQ
tLZ tRCD tRAS tRC   tCAC
tHZ tCAC tCAC tRQL tRP 
 

 
Undefined
CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
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Rev. D 01/28/08
49
IS42S16100
Read Cycle / Page Mode; Data Masking
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE NO PRE BANK 1 tCS tQMD tAC tCH tAC tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMN m
COLUMN n
COLUMN o AUTO PRE BANK 0 AND 1 BANK 0 OR 1 BANK 1 BANK 0
BANK 0
tQMD tAC
tAC tOH
DOUT m+1
tAC tOH
DOUT o
tOH
DOUT n
tOH
DOUT o+1
DQ
tLZ tRCD tRAS tRC   tCAC
tHZ tCAC
tLZ tCAC tRQL tRP 
 
tHZ

 
Undefined
CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
50
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Rev. D 01/28/08
IS42S16100
Write Cycle / Page Mode
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 tCS BANK 0 tCH BANK 0 OR 1 BANK 1 BANK 0 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMN m
COLUMN n
COLUMN o AUTO PRE BANK 0 AND 1
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH tDS DIN n
tDH tDS DIN n+1
DQ
tRCD tRAS tRC 
tDH tDS tDH DIN o DIN o+1 tDPL tRP


 
 
Undefined
CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
51
IS42S16100
Write Cycle / Page Mode; Data Masking
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 BANK 0 NO PRE BANK 1 BANK 0 BANK 1OR 0 BANK 1 BANK 0
(1)
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMN m
COLUMN n
COLUMN o AUTO PRE BANK 0 AND 1
tCS
tCH
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH DIN n
tDS
tDH tDS DIN o
tDH DIN o+1 tDPL tRP
DQ
tRCD tRAS tRC 



 
 
Undefined
CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
52
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Read Cycle / Clock Suspend
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS NO PRE BANK 1 BANK 0 BANK 0 OR 1 tCH BANK 1 BANK 0 tCHI tCL tCKS tCKH
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN m AUTO PRE BANK 0 AND 1
ROW ROW BANK 1 BANK 0
tQMD
tAC
tAC tOH tOH
DOUT m+1 DOUT m
DQ
tLZ tRCD tRAS tRC    tCAC
tHZ tRP tRAS tRC   
  
Undefined
CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
53
IS42S16100
Write Cycle / Clock Suspend
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 BANK 0 tCHI tCL tCKS tCKH
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN m AUTO PRE BANK 0 AND 1
ROW ROW BANK 1 BANK 0
tCH
tDS
tDH DIN m
tDS DIN m+1
tDH
DQ
tRCD tRAS tRC 
tDPL tRP tRAS tRC    
  
Undefined
CAS latency = 2, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
54
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Read Cycle / Precharge Termination
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tQMD tAC tCH tAC tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMN m
ROW ROW BANK 0 OR 1 BANK 0 BANK 0 BANK 1
COLUMN n AUTO PRE NO PRE BANK 1 BANK 0
tAC tOH
DOUT m+1
tHZ tOH
DOUT m+2
DQ
tLZ tRCD tRAS tRC   tCAC
tRQL tRP
tRCD tRAS tRC
tCAC


 
Undefined
CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
55
IS42S16100
Write Cycle / Precharge Termination
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tCH BANK 0 OR 1 BANK 0 tCS tCH BANK 0 ROW BANK 1 NO PRE BANK 1 BANK 0 tCS tDH
DIN 0n
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMN m
ROW
COLUMN n AUTO PRE
tDS
tDH tDS
DIN 0m DIN 0m+1
tDH tDS
DIN 0m+2
tDH
tDS
DQ
tRCD tRAS tRC 
tRCD tRP tRAS tRC  
   
Undefined
CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
56
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Read Cycle / Byte Operation
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 tCH BANK 0 OR 1 BANK 1 tQMD tQMD tAC tLZ BANK 0 BANK 0
(1)
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 UDQM
COLUMN m AUTO PRE BANK 0 AND 1
ROW ROW BANK 1
tCS tCS
tCH tHZ tOH
DOUT m
LDQM
tAC tLZ tAC tOH
DOUT m+2
tOH
DOUT m+3
DQ8-15
tAC tLZ
tAC tOH
DOUT m
tOH
DOUT m+1
DQ0-7
tRCD tRAS tRC     tCAC
tQMD
tRQL tRP
tRCD tRAS tRC 
 
 
Undefined
CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
57
IS42S16100
Write Cycle / Byte Operation
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 tCH BANK 0 OR 1 BANK 1 BANK 0 BANK 0 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 UDQM
COLUMN m AUTO PRE BANK 0 AND 1
ROW ROW BANK 1
tCS tCS
tCH tDS tDH DIN m DIN m+1 tDH DIN m tDS DIN m+3 tDPL tRP      
   tRCD tRAS tRC tDH tDS DIN m+3 tDH
LDQM
tDS tDH
DQ8-15
tDS
DQ0-7
tRCD tRAS tRC 
Undefined
CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
58
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Read Cycle, Write Cycle / Burst Read, Single Write
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tQMD tAC tAC tOH
DOUT m (1) (1)
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 DQM
COLUMN m NO PRE BANK 1
COLUMN n AUTO PRE NO PRE BANK 1 tCH tAC tOH
DOUT m+1
BANK 0 AND 1 BANK 0 OR 1 BANK 1 BANK 0
BANK 0
tAC tOH
DOUT m+2
tDS tOH
DOUT m+3 DIN n
tDH
DQ
tLZ tRCD tRAS tRC   tCAC
tHZ tDPL tRP   
 
Undefined
CAS latency = 2, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
59
IS42S16100
Read Cycle
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 BANK 0 tCS tQMD tAC tAC tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN m BANK 0 AND 1 NO PRE BANK 1 BANK 0 OR 1 BANK 1 tCH BANK 0 tAC tOH
DOUT m+1
ROW ROW BANK 1 BANK 0
tAC tOH
DOUT m+2
tOH
DOUT m+3
DQ
tLZ tRCD tRAS tRC   tCAC
tRQL tRP 
 
tHZ
tRCD tRAS tRC 
Undefined
CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
60
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Read Cycle / Auto-Precharge
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 BANK 0 tCS tQMD tAC tAC tOH
DOUT m (1)
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 DQM
COLUMN AUTO PRE
ROW ROW
BANK 1 tCH tAC tOH
DOUT m+1
BANK 1 BANK 0
tAC tOH
DOUT m+2
tOH
DOUT m+3
DQ
tLZ tRCD tRAS tRC   tCAC
tPQL tRP
tHZ
tRCD tRAS tRC 
Undefined
CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
61
IS42S16100
Read Cycle / Full Page
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 BANK 0 tCS tCH tAC tAC tOH
DOUT 0m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T262
T263
T264
T265
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN NO PRE BANK 0 OR 1 BANK 0
tAC tOH
DOUT 0m+1
tAC tOH
DOUT 0m-1
tAC tOH
DOUT 0m
tOH
DOUT 0m+1
DQ
tLZ
(BANK 0) (BANK 0) (BANK 0)
tRCD
tRAS tRC
(BANK 0)
tCAC
tRBD
(BANK 0)
tHZ tRP




Undefined
CAS latency = 3, burst length = full page Note 1: A8,A9 = Don't Care.
Don't Care
62
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Read Cycle / Ping Pong Operation (Bank Switching)
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 BANK 1 ROW NO PRE BANK 0 tCS tQMD tAC tLZ tAC tOH
DOUT 0m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
ROW
COLUMN AUTO PRE
COLUMN AUTO PRE
ROW ROW
NO PRE BANK 1
BANK 0 OR 1 BANK 0
BANK 0 OR 1 BANK1 tCH tAC tOH
DOUT 0m+1
BANK 0
tAC tOH
DOUT 1m
tOH
DOUT 1m+1
DQ
(BANK 0 TO 1) (BANK 0) (BANK 0) (BANK 0)
tRRD
(BANK 1) (BANK 0)
tRCD
(BANK 1)
tCAC
tHZ
(BANK 0) (BANK 0)
tRCD
tCAC
tRQL tRP
(BANK 0) (BANK 0) (BANK 0)
tRCD tRAS tRC
tRAS tRC
(BANK 1) (BANK 1)
tRAS tRC
(BANK1)
tRP


 
 



Undefined
CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
63
IS42S16100
Write Cycle
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tCH NO PRE BANK 1 BANK 0 OR 1 BANK 1 BANK 0 COLUMN BANK 0 AND 1 ROW BANK 1 BANK 0 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
ROW
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH tDS DIN m+2
tDH DIN m+3 tDPL tRP tRCD tRAS tRC 
DQ
tRCD tRAS tRC 

 
Undefined
CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
64
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Write Cycle / Auto-Precharge
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS BANK 0 tCH BANK 0 BANK 1 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN AUTO PRE
ROW ROW BANK 1
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH tDS DIN m+2
tDH DIN m+3 tDAL tRP tRCD tRAS tRC 
DQ
tRCD tRAS tRC 

Undefined
CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
65
IS42S16100
Write Cycle / Full Page
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS BANK 0 tCH NO PRE BANK 0 OR 1 BANK 0 COLUMN tCHI tCL
T1
T2
T3
T4
T5
T6
T259
T260
T261
T262
T263
T264
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
tDS
tDH tDS DIN 0m
tDH tDS DIN 0m+1
tDH tDS DIN 0m+2
tDH DIN 0m-1 DIN 0m tDPL tRP
DQ
tRCD tRAS tRC 



Undefined
CAS latency = 3, burst length = full page Note 1: A8,A9 = Don't Care.
Don't Care
66
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Write Cycle / Ping-Pong Operation (Bank Switching)
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 BANK 1 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMN AUTO PRE
ROW ROW
COLUMN AUTO PRE
ROW ROW
NO PRE BANK 1
BANK 0 OR 1 BANK 0 BANK 1 BANK 0 tCH
tDS
tDH tDS DIN 0m
tDH tDS DIN 0m+1
tDH tDS DIN 0m+2
tDH tDS DIN 0m+3
(BANK 0)
tDH tDS DIN 1m
tDH tDS DIN 1m+1
tDH tDS DIN 1m+2
tDH DIN 1m+3 tDPL tRCD
DQ
(BANK 0 TO 1) (BANK 0) (BANK 0) (BANK 0)
tRRD
tDPL
tRCD
(BANK 1)
tRCD
tRAS tRC
(BANK 0)
tRP
tRAS tRC
(BANK 1) (BANK 1)
tRAS tRC

 

 


Undefined
CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
67
IS42S16100
Read Cycle / Page Mode
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 1 BANK 0 tCS tQMD BANK 0 NO PRE NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 BANK 0
(1) (1)
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN m
COLUMN n
COLUMN o AUTO PRE BANK 0 AND 1
tCH tAC tAC tOH
DOUT o
tAC tLZ
tAC tOH
DOUT m
tAC tOH
DOUT m+1
tAC tOH
DOUT n
tOH
DOUT n+1
tOH
DOUT o+1
DQ
tRCD tRAS tRC   tCAC tCAC
tCAC tRQL tRP   
 
tHZ

Undefined
CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
68
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Read Cycle / Page Mode; Data Masking
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 BANK 1 BANK 0 tCS tQMD BANK 1 BANK 0 tCH tAC tLZ tAC tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMN m NO PRE
COLUMN n NO PRE
COLUMN o AUTO PRE NO PRE BANK 1 BANK 0 tQMD tAC tOH
DOUT m+1 DOUT n
BANK 0 AND 1 BANK 0 OR 1 BANK 1 BANK 0
tAC tOH
tAC tOH
DOUT o
tOH
DOUT o+1
DQ
tCAC
tCAC tRQL tRP    
 
tHZ
tRCD tRAS tRC  
tCAC

Undefined
CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
69
IS42S16100
Write Cycle / Page Mode
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS BANK 0 BANK 0 tCH NO PRE BANK 1 NO PRE BANK 1 NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 BANK 0 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMN m
COLUMN n
COLUMN o AUTO PRE BANK 0 AND 1
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH DIN n
tDS
tDH tDS DIN o
tDH DIN o+1 tDPL tRP
DQ
tRCD tRAS tRC 



 
 
Undefined
CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
70
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Write Cycle / Page Mode; Data Masking
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 BANK 1 BANK 0 NO PRE BANK 1 BANK 0 BANK 1 BANK 0 NO PRE NO PRE BANK 1 BANK 0 BANK 1OR 0
RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMN m
COLUMN n
COLUMN o AUTO PRE BANK 0 AND 1
tCS
tCH
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH DIN n
tDS
tDH tDS DIN o
tDH DIN o+1 tDPL tRP
DQ
tRCD tRAS tRC 



 
 
Undefined
CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
71
IS42S16100
Read Cycle / Clock Suspend
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
tCKS
tCKH
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 tQMD tCH tAC tAC tOH tOH
DOUT m+1 DOUT m
RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN m AUTO PRE BANK 0 AND 1
BANK 0
DQ
tLZ tRCD tRAS tRC    tCAC
tHZ tRP


 
Undefined
CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
72
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Write Cycle / Clock Suspend
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 tCS NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 BANK 0 tCHI tCL tCKS tCKH
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN m AUTO PRE BANK 0 AND 1
ROW ROW BANK 1 BANK 0
tCH
tDS
tDH DIN m
tDS DIN m+1
tDH
DQ
tRCD tRAS tRC 
tDPL tRP tRAS tRC    
  
Undefined
CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
73
IS42S16100
Read Cycle / Precharge Termination
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tQMD tAC BANK 0 OR 1 BANK 0 tCH BANK 0 ROW BANK 1 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN m
ROW
tAC tOH
DOUT m
tAC tOH
DOUT m+1
tHZ tOH
DOUT m+2
DQ
tLZ tRCD tRAS tRC   tCAC
tRQL tRP
tRCD tRAS tRP


Undefined
CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
74
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Write Cycle / Precharge Termination
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 0 tCS NO PRE BANK 0 tCH BANK 0 OR 1 BANK 0 tCS tCH BANK 0 ROW BANK 1 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN m
ROW
tDS
tDH tDS
DIN 0m DIN 0m+1
tDH tDS
DIN 0m+2
tDH
DQ
tRCD tRAS tRC 
tRCD tRP tRAS tRP  
 
Undefined
CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
75
IS42S16100
Read Cycle / Byte Operation
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 tCS tCS tQMD tQMD tAC tLZ tHZ tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 UDQM
COLUMN m AUTO PRE BANK 0 AND 1
ROW ROW BANK 0 OR 1 BANK 1 tCH BANK 0 BANK 0 BANK 1
tCH tAC tLZ
DOUT m+2
LDQM
tAC tHZ tOH
DOUT m+3
DQ8-15
tAC tLZ
tAC tOH
DOUT m
tHZ tOH
DOUT m+1
DQ0-7
tRCD tRAS tRC     tCAC
tQMD
tRQL tRP
tRCD tRAS tRP 
 
 
Undefined
CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
76
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
Write Cycle / Byte Operation
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 NO PRE BANK 1 BANK 0 BANK 0 OR 1 BANK 1 tCH tCH tDS tDH DIN m tDS tDH DIN m tRCD tRAS tRC       
   DIN m+1 tDS DIN m+3 tDPL tRP tRCD tRAS tRP tDH tDS DIN m+3 tDH BANK 0 BANK 0
RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 UDQM
COLUMN m AUTO PRE BANK 0 AND 1
ROW ROW BANK 1
tCS tCS
LDQM
tDS tDH
DQ8-15
DQ0-7
Undefined
CAS latency = 3, burst length = 4 Note 1: A8,A9 = Don't Care.
Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
77
IS42S16100
Read Cycle, Write Cycle / Burst Read, Single Write
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK 1 BANK 0 BANK 0 tCS tQMD tAC tAC tOH tOH
DOUT m+1 DIN n DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMN m NO PRE BANK 1
COLUMN n AUTO PRE NO PRE BANK 1 BANK 0 tCH BANK 0 AND 1 BANK 0 OR 1 BANK 1 BANK 0
tDS tDH
DQ
tLZ tRC tRAS tRC   tCAC
tHZ tDPL tRP   
 
Undefined
CAS latency = 3, burst length = 2 Note 1: A8,A9 = Don't Care.
Don't Care
78
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
IS42S16100
ORDERING INFORMATION Commercial Range: 0C to 70C
Frequency 200 MHz 166 MHz 143MHz Speed (ns) 5 6 7 Order Part No. IS42S16100-5TL IS42S16100-5BL IS42S16100-6TL IS42S16100-6BL IS42S16100-7TL IS42S16100-7BL Package 400-mil TSOP II, Lead-free 60-ball BGA, Lead-free 400-mil TSOP II, Lead-free 60-ball BGA, Lead-free 400-mil TSOP II, Lead-free 60-ball BGA, Lead-free
Industrial Range: -40C to +85C
Frequency 166 MHz 143MHz Speed (ns) 6 7 Order Part No. IS42S16100-6TLI IS42S16100-6BLI IS42S16100-7TLI IS42S16100-7BLI Package 400-mil TSOP II, Lead-free 60-ball BGA, Lead-free 400-mil TSOP II, Lead-free 60-ball BGA, Lea-free
Please contact the Product Manager for leaded parts support.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 01/28/08
79
PACKAGING INFORMATION
Mini Ball Grid Array Package Code: B (60-Ball)
o 0.40 + +/-0.05 (60X) 1234567 A B C D E F G H J K L M N P R 7654321 A B C D E F G H J K L M N P R
e E1 E
e D D1
A1 SEATING PLANE
A
Notes: 1. Controlling dimensions are in millimeters. 2. 0.65 mm Ball Pitch
mBGA - 10.1mm x 6.4mm
MILLIMETERS Sym. Min.
No. Leads A A1 D D1 E E1 e -- 0.23 10.00 -- 6.30 -- --
INCHES Min. Typ. Max.
Typ. Max.
60 -- 0.28 9.10 6.40 3.90 0.65 1.20 0.33 -- 6.50 -- --
--
--
0.047 0.402 -- 0.256 -- --
0.009 0.011 0.013 0.394 0.398 -- -- -- 0.358 0.154 0.026 0.248 0.252
10.10 10.20
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. D 02/16/06
PACKAGING INFORMATION
Plastic TSOP Package Code: T (Type II)
N
N/2+1
E1
E
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
1 D
N/2
SEATING PLANE
ZD
A
.
e b L A1  C
Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD 
Millimeters Min Max
Inches Min Max
Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0 5 0 5
Millimeters Min Max 50 -- 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0 5
Inches Min Max
(N) 32 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0 5 0 5
-- 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0 5
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. F 06/18/03


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